Samsung: HBM4 has begun shipping to customers

Source: Wall Street Insights

Zhao Ying

Samsung Electronics announced on Thursday that it has begun commercial shipments of its latest generation HBM4 memory chips to customers, marking the company's strategic lead in the highly competitive AI memory chip market. Previously, rival SK Hynix held a leading position in technology and dominated Nvidia's high-bandwidth memory chip orders.

According to Bloomberg, Samsung Electronics announced on Thursday that it has begun commercial shipments of its latest generation HBM4 memory chips to customers, marking the company’s strategic lead in the highly competitive AI memory chip market.

This is an important milestone for Samsung. The company is racing to meet booming demand for Nvidia's graphics chips, which are the most advanced accelerators for training and running AI models. High-bandwidth memory chips are an integral part of AI accelerators.

Previously, rival SK Hynix held a leading position in technology and dominated Nvidia's high-bandwidth memory chip orders. But in recent months, Samsung has closed that gap.

Performance significantly exceeds industry standards

Samsung HBM4 has achieved a significant breakthrough in performance indicators against industry standards. From the beginning of research and development, Samsung has set its goal to exceed the performance standards of JEDEC (Solid State Technology Association), and for this purpose it has adopted both 1c DRAM process and 4nm wafer foundry process.

With this process combination, Samsung HBM4's data processing speed reaches 11.7 Gbps, which is approximately 37% higher than the JEDEC standard 8 Gbps and 22% faster than the 9.6 Gbps of the previous generation HBM3E. The single-stack storage bandwidth reaches 3 TB/s, which is 2.4 times that of the previous generation product.

Using 12-layer stacking technology, Samsung HBM4 can provide 36 GB capacity. In the future, if 16-layer stacking is used, the capacity can be expanded to 48 GB.

This product adopts a low-power design while improving computing performance, which is expected to help data centers reduce power consumption and cooling costs. This has important implications for enterprises operating large-scale AI infrastructure.

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